1. Field of the Invention
The present invention relates to a method of fabricating an integrated circuit capacitor, and more particularly to a method of fabricating a capacitor in a metal-insulator-metal (MIM) structure used in logic or analog circuits of merged dynamic random access memory (DRAM) and logic (MDL) devices.
2. Description of the Prior Art
Semiconductor integrated circuits are generally classified as digital or analog. Digital type integrated circuits (e.g., logic circuits) produce an output according to the state(s) of one or more input signals, whereas analog type integrated circuits (e.g., analog circuits) produce an output according to linearly varied changes in an input signal.
In digital and analog type integrated circuits, data is stored according to the presence or absence of charge accumulated at a capacitor. In order to maintain normal response characteristics, the capacitor should be fabricated in a way that prevent its capacitance from varying with changes in voltage or temperature.
Different from general metallic oxide semiconductor field-effect transistors (MOSFETs) or junction capacitors, MDL capacitors having a polysilicon-insulator-polysilicon (PIP) or metal-insulator-metal (MIM) structure have been proposed because their capacitance does not depend on bias voltage or temperature.
Thin film MIM capacitors, however, do not provide high unit area capacitance in comparison with the PIP capacitors. In addition, MIM capacitors have a lower voltage coefficient of capacitance (VCC), which indicates variation of capacitance according to changes in voltage. They also have a lower temperature coefficient of capacitance (TCC), which indicates variation of capacitance according to changes in temperature. PIP capacitors, for instance, have VCC and TCC values of about 220 parts per million/volt (ppmN) and 120 parts per million/degree Celsius (ppm/C), respectively, but those of MIM capacitors are about 60 ppm/V and 70 ppm/C, respectively. As a result, MIM capacitors have been used for fabricating precise analog products. In recent years, however, there has been a tendency to use MIM capacitors to make logic and analog circuits.
FIGS. 1a through 1g are sequential processing diagrams illustrating a widely used conventional method of fabricating MIM capacitors of a logic or analog circuit of an MDL device. The method will be described with reference to accompanying drawings.
As shown in FIG. 1a, a first inter-level insulating layer 12 is formed on a semiconductor substrate 10 having a lower structure (not shown) consisting of transistors, predetermined wires, and the like.
As shown in FIG. 1b, a first conductivity layer 14 of aluminum (Al) is formed on the first inter-level insulating 12. A capping metal layer of titanium nitride (TiN) 16 is formed to a thickness of about 200 to 600 angstroms (xc3x85) on the first conductivity layer 14. A photo resist layer (not shown) defining capacitor regions is used as a mask for sequentially etching the capping metal layer 16 and the first conductivity layer 14, thereby forming a xe2x80x9cfirst conductivity 14/capping metal layer 16xe2x80x9d deposition structure defining a lower electrode (I).
As shown in FIG. 1c, a second inter-level insulating layer 18 is formed on the first inter-level insulating layer 12 of the lower electrode (I). Then, a chemical mechanical polishing (CMP) or etch-back process is performed to planarize the second inter-level insulating layer 18. Accordingly, in order to expose predetermined portions of the surface of the first conductivity layer 14 of the lower electrode (I), the second inter-level insulating layer 18 and capping metal layer 16 are selectively etched to form a via hole or cavity (h) in the insulating layer 18. In this process, a portion of the first conductivity layer 14 is simultaneously etched away to form a recessed portion in the first conductivity layer 14 on the bottom surface of the via hole (h).
As shown in FIG. 1d, a dielectric layer 20 is formed over the second inter-level insulating layer 18 covering the via hole (h) and a thin blocking metal layer 22 is formed by a xe2x80x9ctitanium/titanium nitridexe2x80x9d (xe2x80x9cTi/TiNxe2x80x9d) deposition on the dielectric layer 20.
As shown in FIG. 1e, a second conductivity layer of tungsten (W) is formed on the structure in order to completely fill in the via hole (h). A CMP or etch-back process is performed on the second conductivity layer in order to expose the surface of the blocking metal layer 22, thereby forming a conductivity plug 24 of W in the via hole (h).
As shown in FIG. 1f, a third conductivity layer 26 of Al alloy is formed on the blocking metal layer 22 having conductivity plug 24. A photo resist pattern (not shown) defining capacitor regions is used as a mask for sequentially etching the third conductivity layer 26, blocking metal layer 22, and the dielectric layer 20 in order to expose predetermined portions of the surface of the second inter-level insulating layer 18. As a result, a conductivity layer of a predetermined size defines an upper electrode (II), thereby completing the fabrication process.
As a consequence, the dielectric layer 20 lies between the xe2x80x9cconductivity plug 24/conductivity layer 26xe2x80x9d deposition structure of the upper electrode (II) on the top thereof and the xe2x80x9cconductivity layer 14/capping metal layer 16xe2x80x9d deposition structure of the lower electrode (I) on the bottom thereof, which forms the MIM capacitor. As described above, the capping metal layer 16 is made of TiN and both edges where the dielectric layer 20 and the lower electrode (I) are contacted is formed in a sharply angled structure.
However, if an MDL capacitor is fabricated by the aforementioned method, problems may occur. These problems are described below.
In forming the via hole (h), the etching process is performed vertically downward to the capping metal layer 16 of the lower electrode (I). When the etching process is completed, the lower and lateral surfaces of the via hole (h) meet in a perpendicular relationship (e.g., at a right angle) at the bottom of via hole (h). FIG. 1g shows an enlarged partial perspective view of the affected area, including the lower surface of the via hole (h).
Along the lower edge of the via hole (h) in the region of the dielectric layer 20 meeting at an angle, there may also exist a step coverage defect, which is manifested by a thinner dielectric layer 20 compared to other regions of the via hole (h).
Current leakage may occur at the step coverage defect during operation of the device. Even worse, a short circuit may occur between upper and lower electrodes, thereby damaging the capacitor and reducing the yield during production of such semiconductor devices.
In addition, the dielectric layer 20 at the step coverage defect is exposed to higher electric field strengths, i.e., called xe2x80x9cconcentration of electric field,xe2x80x9d which occurs in the operating device thereby lowering reliability of products incorporating the fabricated device. Therefore, there is an urgent demand to solve the aforementioned problems.
In view of the above, it is a feature of the present invention to provide a method for fabricating a capacitor of a semiconductor integrated circuit by forming a capping metal layer of xe2x80x9cTi/TiNxe2x80x9d or xe2x80x9cTi/TiWxe2x80x9d depositions which have a higher etching rate than an oxide layer, and by performing an etching process at lower edges of a via hole in a tapered manner in order to equalize or smooth the thickness of the dielectric layer at the bottom of the via hole, thereby preventing reduction in yield due to step coverage defects and improving reliability of devices otherwise subjected to a concentration of electric fields.
In order to accommodate the aforementioned feature, there is provided a method for fabricating a capacitor of a semiconductor integrated circuit comprising the steps of forming a conductivity layer on a semiconductor substrate having a first inter-level insulating layer; forming a capping metal layer with a higher etching rate than an oxide layer on the conductivity layer; forming a lower electrode in a xe2x80x9cconductivity layer/capping metal layerxe2x80x9d deposition structure by etching the capping metal layer and the conductivity layer to expose a predetermined part of the surface of the first inter-level insulating layer; forming a second inter-level insulating layer on the first inter-level insulating layer having the lower electrode; forming a via hole by etching the second inter-level insulating layer and the capping metal layer to expose a predetermined portion of the surface of the lower electrode, wherein a tapered capping metal layer remains along the lower edges of the via hole; and forming an upper electrode and inserting a dielectric layer in at least a portion of the via hole.
A collimator containing a sputtering unit is used to form by deposition the xe2x80x9cTi/TiNxe2x80x9d or xe2x80x9cTi/TiWxe2x80x9d capping metal layer, wherein Ti deposition preferably has a thickness of about 50 to 500 xc3x85 and the TiN or TiW deposition preferably has a thickness of about 100 to 1500 xc3x85.
Furthermore, either a dry etching process or a complex process including a combination of wet and dry etching processes may be used to form the via hole (h). Etching gases CHF3 and CF4 having a mixing ratio of one to X, that is, CHF3:CF4=1:X (where X=0.5 to 2), are used for the dry etching process. The via hole is preferably formed at a horizontal distance of about 100 to 800 xc3x85 from the remaining capping metal layer along the edge of its lower surface.
If a MIM capacitor is fabricated according to the present invention, the difference in the selective etching rate between the second inter-level insulating layer and the capping metal layer prevents the capping metal layer from being vertically etched. Instead, the capping metal layer is etched in a tapered fashion, thereby achieving rounded lower edges at the lower portion of the via hole. Accordingly, forming the dielectric layer as aforementioned provides a dielectric layer have a more even thickness thereby to prevent concentration of an electric field at particular portions of the dielectric layer, as well as to prevent step coverage defects in the dielectric layer.